Stage 03 · Custom ASICs
Design Your Chip
Our reinforcement-learning environment explored tens of thousands of chip designs for a ternary 1.7B-parameter model. Pick a process node, tell it what you care about, power, latency, area, and it hands you the best design it found. Then build it.
Model
Pareto front drag to rotate
Objective weights
Balanced edge design
Power0.00 W
Area0 mm²
Throughput0 tok/s
Silicon
— mm²
this chip · — mm²
iPhone A-series chip · ~100 mm²
Inference throughput
Candidate designs and measurements come straight from our RL search runs, nothing here is mocked. Questions? contact@lamb-labs.com