Lamb Labs is building MPUs (Model Processing Units). We hardcode the entire model, including its weights, into silicon. The model is the chip. This solves the memory-bandwidth bottleneck GPUs face, targeting 20,000+ tokens per second. Backed by Y Combinator.
Fast inference is a full-stack problem. We get more useful tokens out of today’s GPUs, then carry the same obsession with speed and efficiency down into FPGA fabric and custom silicon.
Larry is our one-bit version of Qwen3.8 27B, 14.6× smaller than the original, so the whole model can fit on-chip. It’s the model our first MPU will carry, and you can chat with it live today. Try Larry live.
We turn models into dedicated compute and memory layouts instead of moving every weight through a general-purpose stack. Little Lamb is our smallest end-to-end proof: a model generating text entirely inside FPGA fabric. The Little Lamb demo is temporarily offline.
We quantised Qwen3.8 27B to one bit per weight, shaping the model around one hardware constraint: fitting entirely on-chip. Larry is 3.8 GB, 14.6× smaller than the original weights, and keeps 92% of Qwen’s IFEval strict-prompt score. It’s the model our first MPU carries. The live demo runs it on a single GPU today. Try Larry live.
We compile the model into custom accelerator logic. Our first prototype runs today on an off-the-shelf Kria KV260 board: an 8B-parameter model under 10 W, less power than a lightbulb. This board is the proof that the architecture maps to hardware.
We trained a tiny language model from scratch, then burned its weights into FPGA fabric. It generates every token on a $250 Kria KV260 with all weights resident in on-chip memory and no DRAM in the token loop. It is deliberately tiny; the point is a live, end-to-end proof that a self-trained model can run entirely on-chip. At 12,000 tokens per second, the FPGA can execute 200 token steps during one 16.7 ms refresh interval; the live demo's full 64-token reply takes about 5.3 ms. The live demo is temporarily offline.
Custom silicon for each model, its architecture hard-coded on-chip. Our target: tape out a chip that runs a 27B-parameter model at 20,000+ tokens per second. Our RL environment searches chip designs for the best speed and energy per token.
Email contact@lamb-labs.com, or see our RL chip-design environment.